Fast characterization of parameterized cell library

In Standard cell library based design methodology, maintaining multiple driving strengths for each gate type is critical for timing closure and low power. However, due to formidable burden on library designers, often only a few gate implementations are available for many gate types. The problem becomes more difficult if constructing accurate delay tables is considered. This imposes a great challenge on efficient cell library design. This challenge is tackled in this paper. We propose a fast cell characterization approach for parameterized cell (p-cell) library. By our approach, the layout and the accurate delay table of any integer-sized cell can be automatically generated on the fly solely from the smallest cell without any additional simulations. Thus, dense cell library can be efficiently generated. As a result, significant area can be saved by the synthesis using the dense p-cell library compared to the sparse cell library which is often the case in practice.