DocumentCode
3094857
Title
Dynamic template generation for resource sharing in control and data flow graphs
Author
Zaretsky, David C. ; Mittal, Gaurav ; Dick, Robert P. ; Banerjee, Prith
Author_Institution
Dept. of Electr. Engg. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
fYear
2006
fDate
3-7 Jan. 2006
Abstract
High-level synthesis compilers often produce reoccurring patterns in intermediate CDFGs during translation. By identifying large reoccurring patterns, one may reduce area and communication overhead by efficiently reusing hardware for multiple operations. This paper presents an algorithm for dynamically generating templates of reoccurring patterns for resource sharing in CDFGs. Results show 40-80% resource reduction using small, incremental template growth, and variations within a 5% margin among varying look-ahead depths.
Keywords
data flow graphs; high level synthesis; program compilers; resource allocation; dynamic template generation; high-level synthesis compilers; intermediate control data flow graphs; reoccurring patterns; resource sharing; Computer science; Cost function; Data flow computing; Field programmable gate arrays; Flow graphs; Hardware; High level synthesis; Libraries; Resource management; Routing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-2502-4
Type
conf
DOI
10.1109/VLSID.2006.75
Filename
1581494
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