Die/wafer stacking with reciprocal design symmetry (RDS) for mask reuse in three-dimensional (3D) integration technology

Each stratum in a 3D chip usually requires a unique mask set which increases the mask cost for a multi-strata chip compared to its 2D counterpart. We present a novel design technique using reciprocal design symmetry (RDS) that allows a mask set (or at least a majority of these) to be used for different strata while still achieving vertical placement and connection of different design functionalities. We demonstrate an application of RDS using a detailed example of a 3D dual-core microprocessor with analyses of various design complexity and testability issues, and a comprehensive simulation and comparison of its thermal characteristics. The coarse grained partitioning of self-contained functional units achieved with RDS is suitable for early adoption of 3D technology as well as for long-term application to low cost system integration due to less redesign effort, design tool requirements, and better testability of each stratum before and after bonding.