DocumentCode
3094958
Title
Place and route considerations for voltage interpolated designs
Author
Brownell, Kevin ; Khan, Ali Durlov ; Brooks, David ; Wei, Gu-Yeon
Author_Institution
Sch. of Eng. & Appl. Sci., Harvard Univ., Cambridge, MA
fYear
2009
fDate
16-18 March 2009
Firstpage
594
Lastpage
600
Abstract
Voltage interpolation is a promising post fabrication technique for combating the effects of process variations. The benefits of voltage interpolation are well understood. Its implementation in a VLSI-CAD flow has been considered through the synthesis stage. In this paper we study the implications of place and route on voltage interpolation. We evaluate multiple placement strategies, and conclude that a hybridization of forced placement and cluster boxing techniques results in minimum overhead.
Keywords
CAD; VLSI; integrated circuit design; interpolation; VLSI-CAD flow; cluster; forced placement; hybridization; place considerations; route considerations; voltage interpolated designs; CMOS process; CMOS technology; Circuits; Design engineering; Fabrication; Interpolation; Logic; Low voltage; Sun; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-2952-3
Electronic_ISBN
978-1-4244-2953-0
Type
conf
DOI
10.1109/ISQED.2009.4810361
Filename
4810361
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