Exploring Silicon Nanophotonics in Throughput Architecture

In high-performance throughput processors, the interconnect experiences power and energy bottlenecks due to massive parallelism and ever-increasing memory accesses in emerging workloads. Also, high-performance throughput processors have exposed bandwidth and latency bottlenecks in on-chip interconnect and off-chip memory access. To eliminate such bottlenecks, we propose silicon nanophotonics and 3-D stacking technologies in throughput architecture. It provides higher communication bandwidth and lower latency signaling mechanisms at reduced power. We evaluate a 3-D stacked GPU with 2048 SIMD cores having photonic interconnect. The photonic multiple-writer-single-reader crossbar network with 32-B channel bandwidth on average achieves 91% network power reduction. In addition, it improves average core-to-memory access latency by 59% and 87% for northbound and southbound traffic, respectively. We anticipate that for emerging workloads and microarchitectures the implications of the proposed ideas are far reaching.