• DocumentCode
    3095334
  • Title

    Derating for static timing analysis: Theory and practice

  • Author

    Dasdan, Ali ; Kolay, Santanu ; Yazgan, Mustafa

  • Author_Institution
    Yahoo Inc., Santa Clara, CA
  • fYear
    2009
  • fDate
    16-18 March 2009
  • Firstpage
    719
  • Lastpage
    727
  • Abstract
    Derating is a versatile technique supported by all static timing analysis (STA) tools in industry. In essence, it enables designers to modify any delay or slew computation performed by such tools. Despite this common use in industry, the scientific literature on derating is scarce to none. This has led to its incorrect use, misunderstanding, and even dismissal. This situation has also been exacerbated with the emergence of statistical STA. This paper is our attempt to fill this void in the literature. We review the use of derating in the context of STA, discuss the important issues, and provide answers to its correct use. We also provide experimental results to justify our claims. Our contribution builds a theoretical and practical foundation to help designers get more insight into derating.
  • Keywords
    NAND circuits; SPICE; delays; integrated circuit design; timing; NAND cell; cell timing libraries; derating; industrial SPICE simulator; integrated circuit design; path delays; stage delays; static timing analysis; Capacitance; Circuits; Delay effects; Educational institutions; Electronic design automation and methodology; Flip-flops; Libraries; Manufacturing industries; Timing; Wires; Derating; electronic design automation; static timing analysis; timing library;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-2952-3
  • Electronic_ISBN
    978-1-4244-2953-0
  • Type

    conf

  • DOI
    10.1109/ISQED.2009.4810382
  • Filename
    4810382