• DocumentCode
    3095687
  • Title

    Improving the performance of CAD optimization algorithms using on-line meta-level control

  • Author

    Aine, Sandip ; Chakrabarti, P.P. ; Kumar, Rajeev

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
  • fYear
    2006
  • fDate
    3-7 Jan. 2006
  • Abstract
    We present a profile based meta-reasoning model for parameter control of CAD algorithms working under constrained run-time. We also propose a unified framework, that can take informed decision about the time allocation and parameter adaptation of the algorithm, where there is no hard run-time constraints, instead the quality-time tradeoff is expressed by a utility function. We use the proposed strategy to get an adaptive cooling schedule for the simulated annealing algorithm. Application on two classical NP-hard problems in the VLSI domain, namely, the standard cell placement problem and the circuit partitioning problem shows that significant improvement of quality can be achieved using a profile based control.
  • Keywords
    VLSI; circuit CAD; circuit optimisation; computational complexity; integrated circuit design; simulated annealing; CAD optimization algorithms; NP-hard problems; VLSI domain; annealing algorithm; circuit partitioning problem; meta-reasoning model; run-time constraints; standard cell placement problem; Adaptive control; Automatic control; Computer science; Cooling; Iterative algorithms; Partitioning algorithms; Runtime environment; Simulated annealing; Stochastic processes; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-2502-4
  • Type

    conf

  • DOI
    10.1109/VLSID.2006.105
  • Filename
    1581535