High performance MTCMOS technique for leakage reduction in hybrid SOI-epitaxial technologies with enhanced-mobility PFET header

Author

Das, Koushik K. ; Lo, Shih-Hsien ; Chuang, Ching-Te

Author_Institution

IBM TJ Watson Res. Center, Yorktown Heights, NY, USA

fYear

2006

fDate

3-7 Jan. 2006

Abstract

Power management has become a key constraint in the design of modern digital VLSI chips. Moreover, with minimum transistor dimensions reaching 100-nm and below, traditional scaling has slowed down. The ITRS roadmap has indicated that device mobility enhancement would be necessary to maintain the generational performance improvement in the sub-100nm VLSI era. This paper presents a comprehensive analysis of the popular low-leakage power MTCMOS circuit technique in various emerging technologies with enhanced-mobility PFETs.

Keywords

CMOS digital integrated circuits; VLSI; field effect transistors; integrated circuit design; silicon-on-insulator; device mobility enhancement; digital VLSI chips; enhanced-mobility PFET header; hybrid SOI-epitaxial technologies; multithreshold CMOS technique; power management; Charge carrier processes; Circuits; Electron mobility; Energy management; Semiconductor epitaxial layers; Silicon germanium; Silicon on insulator technology; Substrates; Subthreshold current; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on

ISSN

1063-9667

Print_ISBN

0-7695-2502-4

Type

conf

DOI

10.1109/VLSID.2006.97

Filename

1581549