Deterministic low-latency data transfer across non-integral ratio clock domains

System on a chip (SOC) implementations typically require their functional blocks to run at different clock frequencies in order to better optimize the system performance for a wide variety of applications while staying within the power envelope. The functional blocks are required to exchange data between themselves and with off-chip memory through a shared system interface module. Data transfers across this interface need to occur at low latency and high bandwidth to achieve the targeted chip performance. Also data transfers need to be deterministic to ease post-silicon debug and satisfy lock-step customers. This precludes the use of synchronizers. Fractional clock data transfer (FCDT) is a solution that ensures full determinism while achieving very low latencies. This paper describes the FCDT scheme in general and proposes a sample implementation.