Linear required-arrival-time trees and their construction

Interconnects are dominating VLSI circuit design in deep sub-micron regime. Construction of global routing trees based on required arrival times (RAT) has gained importance over the traditional problem of finding minimum-cost trees. Moreover, recent investigations on the fidelity of delay estimators indicate that the RAT trees with Manhattan distance delay, known as linear RAT trees, are likely to be a viable alternative to buffered trees with Elmore delay model. This paper introduces the linear RAT trees, discusses some related analysis, and proposes a heuristic method for constructing such trees.