Title :
Linear required-arrival-time trees and their construction
Author :
Dasgupta, Parthasarathi ; Yadava, Prashant
Author_Institution :
Indian Inst. of Manage., Kolkata, India
Abstract :
Interconnects are dominating VLSI circuit design in deep sub-micron regime. Construction of global routing trees based on required arrival times (RAT) has gained importance over the traditional problem of finding minimum-cost trees. Moreover, recent investigations on the fidelity of delay estimators indicate that the RAT trees with Manhattan distance delay, known as linear RAT trees, are likely to be a viable alternative to buffered trees with Elmore delay model. This paper introduces the linear RAT trees, discusses some related analysis, and proposes a heuristic method for constructing such trees.
Keywords :
VLSI; integrated circuit design; network routing; trees (mathematics); Elmore delay model; Manhattan distance delay; VLSI circuit design; deep submicron regime; global routing trees; linear RAT trees; linear required-arrival-time trees; Circuit synthesis; Costs; Delay effects; Delay estimation; Delay lines; Integrated circuit interconnections; Routing; Technology management; Timing; Very large scale integration;
Conference_Titel :
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
Print_ISBN :
0-7695-2502-4
DOI :
10.1109/VLSID.2006.111
