Title :
Designing-in device reliability during the development of high-performance CMOS logic technology to 0.13 μm
Author :
Nayak, Deepak ; Hao, Ming-Yin ; Hijab, Raif
Author_Institution :
Adv. Micro Devices Inc., Sunnyvale, CA, USA
Abstract :
During the development of advanced CMOS process technology, the trade-off between high performance and reliability is being made in each generation of technology. In this work, we present these trade-offs as the CMOS devices are scaled from 0.5 μm-generation to 0.13 μm-generation technology
Keywords :
CMOS logic circuits; integrated circuit design; integrated circuit reliability; integrated circuit testing; logic design; logic testing; 0.13 micron; 0.5 micron; CMOS device downscaling; CMOS logic technology; CMOS performance; CMOS process technology; CMOS reliability; designed-in device reliability; Boron; CMOS logic circuits; CMOS process; CMOS technology; Hot carriers; Hybrid junctions; Logic design; Logic devices; Microprocessors; Temperature;
Conference_Titel :
Integrated Reliability Workshop Final Report, 1997 IEEE International
Conference_Location :
Lake Tahoe, CA
Print_ISBN :
0-7803-4205-4
DOI :
10.1109/IRWS.1997.660279
