Hardware-Accelerated NIOS-II Implementation of a Turbo Decoder

This paper presents a hardware accelerated NIOS-II implementation of a Turbo decoder. Firstly, a Matlab prototype consisting of a) an encoder made of a parallel concatenation of two RSC encoders and b) a decoder based on two identical SOVA decoders is constructed. Simulations of the prototype show that the BER decreases for every iteration in the decoder (down to 10^-4), except for low SNR cases (below -5 dB). Secondly, two FPGA implementations of the decoder are described and compared. The first one consists of software executing on a NIOS II/f soft-core processor, while the second one adds hardware acceleration. Computationally demanding parts of the decoder are identified, rescheduled for parallel execution and moved from the software implementation to the hardware accelerator. The decoding process in the hardware accelerated implementation results in approximately the same BER as for the software implementation, but the execution time is decreased by between 34 % and 25 %, when the number of decoding iterations are increased from 1 to 20, respectively. The accelerated implementation increases the number of required resources from 10 to 16%, as compared to the software one.