A 60 GHz PLL synthesizer with an injection locked frequency divider using a fast VCO frequency calibration algorithm

Author

Shima, Tal ; Miyanaga, K. ; Takinami, Koji

Author_Institution

Device Solutions Center, Panasonic Corp., Yokohama, Japan

fYear

2012

fDate

4-7 Dec. 2012

Firstpage

646

Lastpage

648

Abstract

A 60 GHz phase-locked loop (PLL) synthesizer with an injection locked frequency divider (ILFD) is presented. The PLL employs a simple and fast calibration algorithm consisting of the VCO sub-band selection and the adjustment of the ILFD locking range. The proposed PLL is demonstrated using 90 nm CMOS. The calibration process converges within 100 μsec at all 4-channels defined by the Wireless Gigabit Alliance (WiGig).

Keywords

CMOS integrated circuits; calibration; frequency dividers; millimetre wave devices; phase locked loops; voltage-controlled oscillators; CMOS; PLL synthesizer; VCO frequency calibration algorithm; VCO subband selection; Wireless Gigabit Alliance; calibration process; frequency 60 GHz; injection locked frequency divider; phase-locked loop synthesizer; size 90 nm; Calibration; Frequency conversion; Frequency measurement; Frequency synthesizers; Phase locked loops; Synthesizers; Voltage-controlled oscillators; Phase locked loop; calibration; injection locked frequency divider; locking range; synthesizer;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference Proceedings (APMC), 2012 Asia-Pacific

Conference_Location

Kaohsiung

Print_ISBN

978-1-4577-1330-9

Electronic_ISBN

978-1-4577-1331-6

Type

conf

DOI

10.1109/APMC.2012.6421690

Filename

6421690