Synthesis tools and design environment for dynamically reconfigurable FPGAs

Author

Sklyarov, V. ; Lau, N. ; Oliveira, A. ; Melo, A. ; Kondratjuk, K. ; Ferrari, A. ; Monteiro, R. ; Skliarova, I.

Author_Institution

Dept. de Electron. e Telecoms, Aveiro Univ., Portugal

fYear

1998

fDate

30 Sep-3 Oct 1998

Firstpage

46

Lastpage

49

Abstract

This paper discusses a range of problems in architectural and logic synthesis of digital devices and suggests practical approaches, methods, and tools for the automatic translation of a behavioural specification into a hardware implementation using a dynamically reconfigurable FPGA of the XC6200 family. The work described in this paper covers two basic areas. Firstly, new FPGA-oriented methods for behavioural synthesis of virtual digital circuits within predefined scopes are presented Secondly, an integrated design environment for logic synthesis (IDELS) is described which has been implemented as an extension of commercially available tools. IDELS permits synthesis in accordance with the developed design flow and offers very powerful run-time debugging facilities, including support for dynamic reconfiguration

Keywords

circuit CAD; field programmable gate arrays; high level synthesis; IDELS; XC6200 family; automatic translation; behavioural specification; behavioural synthesis; digital devices; dynamically reconfigurable FPGAs; hardware implementation; integrated design environment; logic synthesis; run-time debugging facilities; synthesis tools; virtual digital circuits; Automatic logic units; Digital circuits; Field programmable gate arrays; Hardware; Integrated circuit synthesis; Logic circuits; Logic design; Logic devices; Reconfigurable logic; Runtime;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design, 1998. Proceedings. XI Brazilian Symposium on

Conference_Location

Rio de Janeiro

Print_ISBN

0-8186-8704-5

Type

conf

DOI

10.1109/SBCCI.1998.715408

Filename

715408