DocumentCode
3097359
Title
SiC MOSFET oxide-trap two-way tunneling model
Author
Lelis, Aivars ; Habersat, D. ; Green, Ron ; Goldsman, N.
Author_Institution
Sensors & Electron Devices Directorate, U.S. Army Res. Lab., Adelphi, MD, USA
fYear
2011
fDate
7-9 Dec. 2011
Firstpage
1
Lastpage
2
Abstract
This work reports the development of a simultaneous two-way tunneling model, based on an existing one-way tunneling model, to simulate the time-dependent and field-dependent charging and discharging of the near-interfacial oxide traps in response to an applied gate-bias stress. It is important that a two-way model be used, since depending on the electric field in the oxide and the distribution of charged and uncharged traps at a given spatial depth, electrons are likely to be both tunneling in and out simultaneously during a given period of time. This model is applied to both the bias stress periods, as well as during the measurement periods, when the gate-to-source voltage is being ramped.
Keywords
MOSFET; semiconductor device models; silicon compounds; MOSFET; SiC; applied gate-bias stress; bias stress periods; field-dependent charging; near-interfacial oxide traps; oxide-trap two-way tunneling model; time-dependent charging; Charge measurement; Electron traps; Logic gates; Silicon carbide; Stress; Tunneling; USA Councils;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Device Research Symposium (ISDRS), 2011 International
Conference_Location
College Park, MD
Print_ISBN
978-1-4577-1755-0
Type
conf
DOI
10.1109/ISDRS.2011.6135139
Filename
6135139
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