Technological and design constraints for multilevel flash memories

Author

Calligaro, C. ; Manstretta, A. ; Modelli, A. ; Torelli, G.

Author_Institution

Dipt. di Elettronica, Pavia Univ., Italy

Volume

2

fYear

1996

fDate

13-16 Oct 1996

Firstpage

1005

Abstract

This paper discusses basic constraints for multilevel storage in flash memories. Aspects such as programming algorithms, threshold voltage distribution, data retention, read disturbs, sense amplifier sensitivity and cell transconductance spread are considered. Experimental results and design considerations are provided. Guidelines for the evaluation of multilevel storage feasibility are given. The feasibility of four-level storage with present technologies using a read voltage around 6 V is demonstrated

Keywords

EPROM; PLD programming; integrated circuit design; integrated circuit reliability; integrated memory circuits; 6 V; cell transconductance spread; data retention; design constraints; four-level storage; multilevel flash memories; programming algorithms; read disturbs; sense amplifier sensitivity; threshold voltage distribution; CMOS technology; Consumer electronics; Distributed amplifiers; Electrons; Flash memory; Guidelines; Linear programming; Microelectronics; Nonvolatile memory; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on

Conference_Location

Rodos

Print_ISBN

0-7803-3650-X

Type

conf

DOI

10.1109/ICECS.1996.584556

Filename

584556