DocumentCode
309737
Title
Design of a low power 7-bit serial counter with energy economized pass-transistor logic (EEPL)
Author
Song, Minkyu ; Kang, Geunsoon ; Kim, Seongwon ; Joe, Euro ; Kang, Bongsoon
Author_Institution
Micro Devices Bus., Samsung Electron. Co. Ltd., South Korea
Volume
2
fYear
1996
fDate
13-16 Oct 1996
Firstpage
1033
Abstract
Energy Economized Pass-transistor Logic (EEPL) is proposed. Adopting the principle of regenerative positive feedback with pMOS switches, we reduce the power in comparison with CPL and SRPL. To demonstrate the performance of EEPL, a low power 7-bit serial counter is designed. The operating speed is about 250 MHz with 0.6 μm 3.3 V CMOS process
Keywords
CMOS logic circuits; counting circuits; 0.6 micron; 250 MHz; 3.3 V; 7 bit; CMOS process; EEPL; design; energy economized pass-transistor logic; low power serial counter; pMOS switch; regenerative positive feedback; CMOS process; Counting circuits; Delay; Energy consumption; Feedback; Inverters; Logic design; Logic devices; MOS devices; Power system restoration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on
Conference_Location
Rodos
Print_ISBN
0-7803-3650-X
Type
conf
DOI
10.1109/ICECS.1996.584563
Filename
584563
Link To Document