DocumentCode
3097512
Title
CVF-coverification framework
Author
Garcez, E.H.A. ; Rosenstiel, Wolfgang
Author_Institution
Tubingen Univ., Germany
fYear
1998
fDate
30 Sep-3 Oct 1998
Firstpage
103
Lastpage
106
Abstract
Nowadays hardware/software codesign is consolidated as a research area However there is a lack of formal verification approaches, which are specially suitable to hardware and software. In this paper we present our coverification framework CVF, which consists of a system able to verify partitioned HW/SW systems using temporal logic model checking as a verification technique
Keywords
formal verification; hardware-software codesign; temporal logic; CVF; coverification framework; formal verification approaches; hardware/software codesign; partitioned HW/SW systems; temporal logic model checking; Boolean functions; Control systems; Data structures; Formal verification; Hardware; Logic; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuit Design, 1998. Proceedings. XI Brazilian Symposium on
Conference_Location
Rio de Janeiro
Print_ISBN
0-8186-8704-5
Type
conf
DOI
10.1109/SBCCI.1998.715420
Filename
715420
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