Efficient IC design of SC decimation filters

Author

Baruqui, F.A.P. ; Petraglia, A. ; Franca, J.E. ; Mitra, S.K.

Author_Institution

Programa de Engenharia Electrica COPPE, Rio de Janeiro, Brazil

fYear

1998

fDate

30 Sep-3 Oct 1998

Firstpage

129

Lastpage

132

Abstract

This paper presents the design steps considered in the development of an integrated circuit for a switched-capacitor decimation filter, for practical application in telecommunication systems, for a sampling rate reduction from 48.20 MHz to 16.07 MHz. The design consists of dimensioning the operational amplifiers, capacitances and analog switches, using a supply voltage of 5 V for a 0.8 μm AMS process. Also shown are electrical simulations using SPECTRE and layout detail design. The filter dissipates approximately 46 mW (including the output buffer) at 5 V, and presents a flat frequency response within 0.12 dB from dc to 3.56 MHz

Keywords

active filters; circuit layout CAD; circuit simulation; frequency response; integrated circuit design; operational amplifiers; switched capacitor filters; telecommunication equipment; 0 to 3.56 MHz; 0.8 micron; 16.07 MHz; 46 mW; 5 V; AMS process; IC design; SC decimation filters; SPECTRE; electrical simulations; flat frequency response; layout detail design; operational amplifiers; output buffer; sampling rate reduction; telecommunication systems; Application specific integrated circuits; Capacitance; Filters; Frequency response; Operational amplifiers; Sampling methods; Switches; Switching circuits; Telecommunication switching; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design, 1998. Proceedings. XI Brazilian Symposium on

Conference_Location

Rio de Janeiro

Print_ISBN

0-8186-8704-5

Type

conf

DOI

10.1109/SBCCI.1998.715426

Filename

715426