DocumentCode :
3097683
Title :
Designing the dispatch stage of a superscalar microprocessor
Author :
Alcantara, Joao M S ; Alves, Vladimir C. ; Filho, Eliseu M C
Author_Institution :
COPPE, Fed. Univ. of Rio de Janeiro, Brazil
fYear :
1998
fDate :
30 Sep-3 Oct 1998
Firstpage :
150
Lastpage :
153
Abstract :
The design of a superscalar microprocessor poses several challenging problems concerning both its architectural conception and VLSI implementation. This paper discusses the main aspects in the design of the dispatch stage of the Superflux superscalar processor. First, it presents a methodology directed to the cooperative development of a large VLSI project. Then, it shows how the methodology is applied to the design of Superflux´s dispatch stage. The approach described can be immediately applied or easily adapted/extended to other large VLSI designs. Although superscalar processors are now present in systems from microcomputers to large multiprocessors, few papers have been published about the practical design of these devices. This paper contributes with an introductory view to this task
Keywords :
VLSI; integrated circuit design; microprocessor chips; multiprocessing systems; parallel architectures; pipeline processing; Superflux superscalar processor; VLSI implementation; architectural conception; dispatch stage; multiprocessors; Cache memory; Clocks; Decoding; Dynamic scheduling; Electrical capacitance tomography; Microprocessors; Pipeline processing; Processor scheduling; Read only memory; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Circuit Design, 1998. Proceedings. XI Brazilian Symposium on
Conference_Location :
Rio de Janeiro
Print_ISBN :
0-8186-8704-5
Type :
conf
DOI :
10.1109/SBCCI.1998.715429
Filename :
715429
Link To Document :
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