A high-performance switching element for a multistage interconnection network

This paper describes the design of the switching element of the multistage interconnection network used within Multiplus, a distributed shared memory multiprocessor. The switching element consists of a 2×2 crossbar switch, FIFO buffers at each input, arbitration and some additional control logic. Its first implementation has been carried out using Altera EPLDs and the Max+PlusII system. The implementation described in this paper is targeted to AMS 0.8 μ/5 V double-metal CMOS technology and uses Synopsys tools to perform the logic synthesis step. This implementation is expected to provide better performance since a faster technology and larger FIFO input buffers are used. In fact, the critical path analysis within the designed circuit indicates that the new switching element implementation will be able to operate with a clock frequency 2.4 times higher than the previous EPLD implementation. In addition, the new switching element provides hardware support to message broadcasting which is expected to enhance Multiplus performance