Advanced Encryption Standard Implemented on FPGA

Author

Hiremath, Sujatha ; Suma, M.S.

Author_Institution

E&C Dept., R.V. Coll. of Eng., Bangalore, India

Volume

2

fYear

2009

fDate

28-30 Dec. 2009

Firstpage

656

Lastpage

660

Abstract

Advanced encryption standard (AES), a Federal Information Processing Standard (FIPS), and categorized as Computer Security Standard. The AES algorithm is a block cipher that can encrypt and decrypt digital information. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits. The Rijndael cipher has been selected as the official Advanced Encryption Standard (AES) and it is well suited for hardware. This paper talks of AES 128 bit block and 128 bit cipher key and is implemented on Spartan 3 FPGA. Synthesis results in the use of 2509 slices, 712 Flip flops, and 4762- 4 input Look Up Tables. The design target is optimization of speed and cost.

Keywords

cryptography; field programmable gate arrays; Computer Security Standard; Federal Information Processing Standard; Spartan 3 FPGA; advanced encryption standard; block cipher; cryptographic keys; digital information; Computer security; Cryptography; Field programmable gate arrays; Galois fields; Hardware; Information processing; Matrices; Niobium; Polynomials; Standards; FPGA; Rijndael algorithm; VHDL;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer and Electrical Engineering, 2009. ICCEE '09. Second International Conference on

Conference_Location

Dubai

Print_ISBN

978-1-4244-5365-8

Electronic_ISBN

978-0-7695-3925-6

Type

conf

DOI

10.1109/ICCEE.2009.231

Filename

5380548