A fair queueing architecture for ATM switches with input buffers

Author

Shimojo, Yoshimitsu

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

2

fYear

1996

fDate

18-22 Nov 1996

Firstpage

830

Abstract

The available bit rate (ABR) and unspecified bit rate (UBR) are reservationless service categories at the ATM layer. ATM switches are required to have large cell buffers to provide such services. A new queueing architecture named Kago for the large input buffer switch is proposed. Kago provides per-VC fair scheduling among the multiple input buffers. The mechanism is divided among several blocks, and is executed in a distributed manner. The volume of processing by each block has little dependence on the number of input buffers and the number of VCs. From the simulation results, it is shown that each VC obtains fair bandwidth regardless of its input port

Keywords

asynchronous transfer mode; buffer storage; queueing theory; scheduling; ABR; ATM switches; FIFO queue; Kago; UBR; available bit rate; cell buffers; fair bandwidth; fair queueing architecture; input buffer switch; input port; multiple input buffers; per-VC fair scheduling; processing volume; reservationless services; simulation results; unspecified bit rate; Asynchronous transfer mode; Bandwidth; Bit rate; Feedback; Robustness; Switches; Telecommunication traffic; Throughput; Traffic control; Virtual colonoscopy;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 1996. GLOBECOM '96. 'Communications: The Key to Global Prosperity

Conference_Location

London

Print_ISBN

0-7803-3336-5

Type

conf

DOI

10.1109/GLOCOM.1996.585983

Filename

585983