Exploring concurrency in data path functional units BIST plan optimization: a study-case

Author

Amazonas, J. ; Strum, Marius ; Chau, Wang Jiang

Author_Institution

Escola Politecnica, Sao Paulo Univ., Brazil

fYear

1998

fDate

30 Sep-3 Oct 1998

Firstpage

244

Lastpage

247

Abstract

This paper presents a procedure to optimize the parallel test plan of all functional units present in a data path. Our algorithm defines which registers will be transformed into test pattern generators (TPGs) and signature analyzers (SAs), minimizing a test cost function. Cellular automata (CAs) registers will be used both for TPG and SA. Very good results were obtained for the tested architectures. A comparison between the parallel test and a serial test has shown a large test time reduction with a small hardware penalty. This procedure is part of an ongoing research which consists of the development of tools to automatically generate BIST testable circuits for architectures synthesized by the MACH high-level synthesis system

Keywords

automatic test pattern generation; built-in self test; cellular automata; high level synthesis; logic testing; scheduling; BIST plan optimization; MACH high-level synthesis system; cellular automata registers; concurrency; data path functional units; functional units; parallel test; serial test; signature analyzers; test cost function; test pattern generators; test time reduction; Algorithm design and analysis; Automatic testing; Built-in self-test; Circuit testing; Concurrent computing; Content addressable storage; Cost function; Hardware; Pattern analysis; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design, 1998. Proceedings. XI Brazilian Symposium on

Conference_Location

Rio de Janeiro

Print_ISBN

0-8186-8704-5

Type

conf

DOI

10.1109/SBCCI.1998.715451

Filename

715451