Input driven synthesis of PLDs and PGAs

The paper presents a fast and efficient algorithm for synthesis of Boolean functions on Xilinx and PAL devices. It starts from lexicographical factorized trees and performs a partitioning of these aces defined by `input slices´. This allows the creation of subfunctions depending on identical subsets of inputs which can then be easily clustered into the same physical device. Results are shown for a large set of benchmarks and compared with the best existing results available both in terms of the number of devices and the depth related to the critical path