Efficient verification of sequential circuits on a parallel system

The paper presents a method to verify functional correctness of FSMs on a parallel system. The equivalence condition is expressed in theoretical terms within the framework of the product machine. It consists in proving that a set of states of the product machine is unreachable from the initial reset state. The algorithm is based on state-of-the-art simulation techniques for explicit enumeration on the inputs and is implemented on a parallel machine. The states of the product machine are partitioned for evaluation among available processors. Experimental results show that the method is applicable to real-world circuits and that the parallel version achieves an almost linear speedup in the number of processors