DocumentCode
3098270
Title
Parallelism extraction and programme restructuring of VHDL for parallel simulation
Author
Vellandi, Beverly ; Lightner, Michael
Author_Institution
Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
fYear
1992
fDate
16-19 Mar 1992
Firstpage
81
Lastpage
87
Abstract
The authors obtained an overall increase in parallelism during VHDL simulation by decomposing simulation models into smaller computational units to be executed in parallel and by parallelizing the simulation support functions. The authors implementation targeted massively parallel architectures. Simulation experimentation and instrumentation was done on the SIMD Connection Machine
Keywords
circuit analysis computing; discrete event simulation; logic CAD; parallel programming; shared memory systems; Connection Machine; LAMPO; SIMD; VHDL simulation; massively parallel architectures; parallel simulation; simulation support functions; Computational modeling; Computer architecture; Computer simulation; Concurrent computing; Delay; Discrete event simulation; Parallel processing; Signal processing; Signal resolution; Steady-state;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location
Brussels
Print_ISBN
0-8186-2645-3
Type
conf
DOI
10.1109/EDAC.1992.205899
Filename
205899
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