DocumentCode :
3098455
Title :
Testing embedded single and multi-port RAMs using BIST and boundary scan
Author :
Alves, V. Castro ; Lubaszewski, M.S. ; Nicolaidis, M. ; Courtois, B.
Author_Institution :
IMAG/TIMA Lab., Grenoble, France
fYear :
1992
fDate :
16-19 Mar 1992
Firstpage :
159
Lastpage :
163
Abstract :
The paper presents a general BIST scheme for the test of RAMs (single and multi-port) embedded in very complex ASICs. A simple BIST circuit driven by the IEEE standard for the boundary scan (BS) is shared by all the memories that are tested simultaneously. The area overhead is greatly compensated by the test development time reduction and the link with BS
Keywords :
VLSI; application specific integrated circuits; automatic testing; boundary scan testing; built-in self test; electronic engineering computing; random-access storage; ASICs; BIST circuit; IEEE standard; area overhead; boundary scan standard; built in self test; embedded RAM; embedded multi port RAM; Application specific integrated circuits; Built-in self-test; Circuit faults; Circuit testing; Design engineering; Integrated circuit testing; Laboratories; Libraries; Random access memory; Read-write memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location :
Brussels
Print_ISBN :
0-8186-2645-3
Type :
conf
DOI :
10.1109/EDAC.1992.205914
Filename :
205914
Link To Document :
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