Compact analytical modeling of the gate leakage current partitioning for Double Gate MOSFET device

Author

Darbandy, Ghader ; Lime, François ; Cerdeira, Antonio ; Estrada, Magali ; Garduño, Salvador Ivan ; Iñiguez, Benjamin

Author_Institution

Dept. d´´Eng. Electron., Electr. i Autom., Univ. Rovira i Virgili, Tarragona, Spain

fYear

2011

fDate

7-9 Dec. 2011

Firstpage

1

Lastpage

2

Abstract

In this paper, we have developed and analyzed a compact gate leakage current partitioning model for Nanoscale Double Gate MOSFETs, assuming the gate current is due to direct tunneling. We have considered the cases of one high k dielectric layer (as an ideal case) and two layers (high k dielectric materials as an insulator with a thin layer of SiO₂ as an interfacial layer). The model calculations show a good agreement with 2D TCAD numerical device simulations (Silvaco ATLAS).

Keywords

CAD; MOSFET; high-k dielectric thin films; leakage currents; 2D TCAD numerical device simulation; compact analytical modeling; compact gate leakage current partitioning model; direct tunneling; double gate MOSFET device; gate leakage current partitioning; high k dielectric layer; high k dielectric material; insulator; interfacial layer; nanoscale double gate MOSFET; Adaptation models; Analytical models; Leakage current; Logic gates; MOSFET circuits; Numerical models; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium (ISDRS), 2011 International

Conference_Location

College Park, MD

Print_ISBN

978-1-4577-1755-0

Type

conf

DOI

10.1109/ISDRS.2011.6135198

Filename

6135198