Title :
An ultra low voltage amplifier design using forward body bias folded cascode topology for 5GHz application
Author :
Karimi, Gh R. ; Nazari, E.
Author_Institution :
Electr. Eng. Dept., Razi Univ., Kermanshah, Iran
Abstract :
In this paper a very low-voltage design method for a 5 GHz folded cascade topology amplifier is presented. Comparing to the conventional cascade topology our design has a better performance regarding the amplifier´s power dissipation (8 mW for a 0.7 V power supply) and its high gain (20.8 dB). Circuit simulations by the use of H-Spice and a standard TSMC 0.18 um CMOS technology confirmed our design goals. The paper presents the tradeoffs involved in the circuit design and the design for performance issues.
Keywords :
CMOS integrated circuits; amplifiers; cascade networks; low-power electronics; network topology; CMOS technology; H-Spice; TSMC; forward body bias folded cascade topology; frequency 5 GHz; gain 20.8 dB; power 8 mW; size 0.18 mum; ultra low voltage amplifier design; very low-voltage design method; voltage 0.7 V; CMOS technology; Circuit simulation; Circuit synthesis; Circuit topology; Design methodology; High power amplifiers; Low voltage; Performance gain; Power dissipation; Power supplies; Forward body bias; folded cascode; low voltage;
Conference_Titel :
Industrial Electronics and Applications (ICIEA), 2010 the 5th IEEE Conference on
Conference_Location :
Taichung
Print_ISBN :
978-1-4244-5045-9
Electronic_ISBN :
978-1-4244-5046-6
DOI :
10.1109/ICIEA.2010.5515393
