The fabrication of poly-Si MOSFETs using ultra-thin high-K/metal-gate stack for monolithic 3D integrated circuits technology applications

Author

Wu, T.H. ; Lee, M.H.

Author_Institution

Inst. of Electro-Opt. Sci. & Technol., Nat. Taiwan Normal Univ., Taipei, Taiwan

fYear

2011

fDate

7-9 Dec. 2011

Firstpage

1

Lastpage

2

Abstract

In conclusion, the MOSFETs using ultra-thin High-K/metal gate stack is compatible for monolithic 3D-ICs process with highest thermal budget 700°C. We proposed the HK/MG poly-Si MOSFET be a candidate to pave a way for future monolithic 3D-ICs applications. Finally, the authors are very grateful for funding support by National Science Council, (NSC 98-2221-E-003 020-MY3), National Taiwan Normal University (NTNU100-D-01) and experimental support by National Nano Device Laboratories (NDL), Taiwan.

Keywords

MOSFET; elemental semiconductors; high-k dielectric thin films; silicon; three-dimensional integrated circuits; NDL; NSC 98-2221-E-003 020-MY3; NTNU100-D-01; National Nano Device Laboratories; National Science Council; National Taiwan Normal University; Si; monolithic 3D integrated circuit technology; polysilicon MOSFET fabrication; ultrathin high-K-metal gate stack; Educational institutions; Grain boundaries; High K dielectric materials; Logic gates; MOSFETs; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium (ISDRS), 2011 International

Conference_Location

College Park, MD

Print_ISBN

978-1-4577-1755-0

Type

conf

DOI

10.1109/ISDRS.2011.6135219

Filename

6135219