Synthesis of sequential circuits for parallel scan

Sequential circuit testing is known to be a difficult problem. The authors present a synthesis for testability (SFT) method to solve this problem. In this approach, some testability features analogous to the traditional scan design are added to the normal logic equations which define the finite state machine (FSM). The augmented FSM is then synthesized with these added features built in. The overhead may thus be reduced as the logic needed to obtain testability is merged with the logic needed for normal functionality. Another advantage of this approach is that the test set length is usually very small; in many cases, the authors obtain a sequential test which is roughly only twice the size of the combinational test set derived for the combinational logic of the sequential circuit. This drastically reduces the test application time without sacrificing the advantages of scan design: high fault coverage and low test generation time. By applying their method to benchmark FSM examples the authors show that the resultant area overhead is also quite low