DocumentCode :
3099138
Title :
Partial strength ordering applied to symbolic switch-level analysis
Author :
Verlind, E. ; Claesen, L. ; Genoe, M. ; Proesmans, F. ; De Man, H.
Author_Institution :
IMEC, Leuven, Belgium
fYear :
1992
fDate :
16-19 Mar 1992
Firstpage :
388
Lastpage :
392
Abstract :
Presents the application of partially ordered strength sets within the symbolic switch-level analysis of digital MOS circuits, where until now only a straightforward approach using a total ordering was used. The paper gives a mathematical formulation for the analysis. The method has been implemented within the existing switch-level analyzer ANAMOS, and has been applied successfully to practical circuits
Keywords :
MOS integrated circuits; circuit analysis computing; digital integrated circuits; logic CAD; ANAMOS; digital MOS circuits; mathematical formulation; partially ordered strength sets; symbolic switch-level analysis; Analytical models; Capacitance; Circuit analysis; Circuit simulation; Logic; Performance analysis; Resistors; Switching circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location :
Brussels
Print_ISBN :
0-8186-2645-3
Type :
conf
DOI :
10.1109/EDAC.1992.205961
Filename :
205961
Link To Document :
بازگشت