Title :
Test generation for C-testable one-dimensional CMOS ILA´s without observable vertical outputs
Author :
Hert, Vladimir ; van de Goor, A.J.
Author_Institution :
Dept. of Comput., Czechoslovak Tech. Univ., Prague, Czechoslovakia
Abstract :
Sufficient conditions for C-testability of one-dimensional CMOS iterative logic arrays without vertical outputs are given in the paper. Stuck-open faults in a cell are detected by pairs of input patterns with Hamming distance 1. Procedure that generates pairs or triples of C-test vectors for a CMOS ILA is introduced. The flow table augmentation procedure which requires an addition of at most three columns to an original flow table and enables the design of C-testable CMOS ILA´s is given
Keywords :
CMOS integrated circuits; automatic testing; fault location; integrated circuit testing; logic arrays; C-test vectors; C-testability; Hamming distance; flow table augmentation procedure; input patterns; one-dimensional CMOS iterative logic arrays; stuck open faults; test generation; CMOS logic circuits; CMOS process; CMOS technology; Fault diagnosis; Hamming distance; Logic arrays; Paper technology; Process design; Testing; Very large scale integration;
Conference_Titel :
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location :
Brussels
Print_ISBN :
0-8186-2645-3
DOI :
10.1109/EDAC.1992.205969
