Parallel sequence fault simulation for synchronous sequential circuits

Author

Kung, Chen-Pin ; Lin, Chen-Shang

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

1992

fDate

16-19 Mar 1992

Firstpage

434

Lastpage

438

Abstract

A novel parallel sequence fault simulation (PSF) algorithm for synchronous sequential circuits is presented. The algorithm partitions a given test sequence into subsequences of equal length and then performs fault simulation with these subsequences in parallel. To overcome the state dependency of sequential circuits, a multiple-pass method is developed to use minimal simulation passes. The experimental results of PSF on the benchmark circuits show that the speedup ratio over a serial sequence fault simulator is 6.6 on average for random test sequences

Keywords

circuit analysis computing; digital simulation; fault location; parallel algorithms; sequential circuits; benchmark circuits; equal length subsequences; minimal simulation passes; multiple-pass method; parallel sequence fault simulation; speedup ratio; state dependency; synchronous sequential circuits; test sequence partitioning; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Logic; Partitioning algorithms; Performance evaluation; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 1992. Proceedings., [3rd] European Conference on

Conference_Location

Brussels

Print_ISBN

0-8186-2645-3

Type

conf

DOI

10.1109/EDAC.1992.205971

Filename

205971