Automated extraction of parasitic BJTs for CMOS I/O circuits under ESD stress

The layout of chip I/O heavily relies on design expertise and guidelines due to the lack of supporting CAD tools. Visual inspection of layout by experts to pinpoint design or layout flaws is common industrial practice for I/O verification. In order to meet industrial demand for I/O verification tools, we have developed a layout extractor which targets the reliability issues of CMOS chip I/Os, with specific emphasis on electrostatic discharge (ESD). In this paper, we present an automated systematic approach for identification of parasitic bipolar junction transistors (BJTs) under ESD stress. The extracted circuit netlist can be simulated by an ESD circuit-level simulator