Automated extraction of parasitic BJTs for CMOS I/O circuits under ESD stress

Author

Li, Tong ; Huh, Yoonjong ; Kang, Sung-Mo

Author_Institution

Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

fYear

1997

fDate

13-16 Oct 1997

Firstpage

103

Lastpage

109

Abstract

The layout of chip I/O heavily relies on design expertise and guidelines due to the lack of supporting CAD tools. Visual inspection of layout by experts to pinpoint design or layout flaws is common industrial practice for I/O verification. In order to meet industrial demand for I/O verification tools, we have developed a layout extractor which targets the reliability issues of CMOS chip I/Os, with specific emphasis on electrostatic discharge (ESD). In this paper, we present an automated systematic approach for identification of parasitic bipolar junction transistors (BJTs) under ESD stress. The extracted circuit netlist can be simulated by an ESD circuit-level simulator

Keywords

CMOS integrated circuits; circuit analysis computing; circuit layout CAD; electrostatic discharge; integrated circuit layout; integrated circuit reliability; software tools; CAD tools; CMOS I/O circuits; CMOS chip I/Os; ESD; ESD circuit-level simulator; ESD stress; I/O verification; automated parasitic BJT extraction; chip I/O layout; circuit netlist; design expertise; design flaws; design guidelines; electrostatic discharge; layout extractor; layout flaws; parasitic BJTs; parasitic bipolar junction transistors; reliability; visual layout inspection; Circuit simulation; Design automation; Electrostatic discharge; Electrothermal effects; Guidelines; Inspection; Protection; Resistors; Semiconductor diodes; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 1997 IEEE International

Conference_Location

Lake Tahoe, CA

Print_ISBN

0-7803-4205-4

Type

conf

DOI

10.1109/IRWS.1997.660296

Filename

660296