Energy-efficient dual array capacitive DAC and switch control for SAR ADC

A new switch control method for a capacitive DAC architecture has been presented. This has been implemented to make a successive approximation register (SAR) ADC more energy efficient. By splitting the capacitor array into two equal halves and using a unity gain buffer, the proposed architecture reduces the switching energy by 97 percent compared to the conventional switching method. The proposed method is analyzed theoretically and then simulations are performed in a 0.18 μm CMOS process to verify the theoretical analysis.