Energy-efficient dual array capacitive DAC and switch control for SAR ADC

Author

Dey, Abhisek ; Bhattacharyya, T.K.

Author_Institution

Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, India

Volume

3

fYear

2011

fDate

11-13 March 2011

Firstpage

366

Lastpage

370

Abstract

A new switch control method for a capacitive DAC architecture has been presented. This has been implemented to make a successive approximation register (SAR) ADC more energy efficient. By splitting the capacitor array into two equal halves and using a unity gain buffer, the proposed architecture reduces the switching energy by 97 percent compared to the conventional switching method. The proposed method is analyzed theoretically and then simulations are performed in a 0.18 μm CMOS process to verify the theoretical analysis.

Keywords

CMOS integrated circuits; analogue-digital conversion; capacitors; digital-analogue conversion; time-varying systems; CMOS process; SAR ADC; capacitor array splitting; energy-efficient dual array capacitive DAC architecture; size 0.18 mum; successive approximation register; switch control; switch control method; unity gain buffer; Arrays; CMOS integrated circuits; Capacitors; Clocks; Energy efficiency; Switches; ADC; SAR; capacitive DAC; switching energy; unity gain buffer;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Research and Development (ICCRD), 2011 3rd International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-61284-839-6

Type

conf

DOI

10.1109/ICCRD.2011.5764215

Filename

5764215