DocumentCode
3099529
Title
64 kB sum-addressed-memory cache with 1.6 ns cycle and 2.6 ns latency
Author
Heald, R. ; Shin, K. ; Reddy, V. ; Kao, I.-F. ; Khan, M. ; Lynch, W. ; Lauterbach, G. ; Petolino, J.
Author_Institution
Sun Microelectron., Palo Alto, CA, USA
fYear
1998
fDate
5-7 Feb. 1998
Firstpage
350
Lastpage
351
Abstract
This circuit combines a sum-addressed-memory (SAM) cache with delayed-reset logic circuitry, enabling cache access with a two-cycle-latency for a 6OO MHz third-generation superscalar processor implementing the Sparc V9 64b architecture.
Keywords
cache storage; 64 kB; Sparc V9 architecture; cache access; delayed-reset logic circuitry; sum-addressed-memory cache; third-generation superscalar processor; two-cycle-latency; Circuits; Decoding; Delay; Logic design; Logic devices; Logic testing; Microelectronics; Performance evaluation; Sun; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-4344-1
Type
conf
DOI
10.1109/ISSCC.1998.672519
Filename
672519
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