• DocumentCode
    3099532
  • Title

    Resources restricted aggressive scheduling

  • Author

    Yeung, Ping F. ; Rees, David J.

  • Author_Institution
    Dept. of Comput. Sci., Edinburgh Univ., UK
  • fYear
    1992
  • fDate
    16-19 Mar 1992
  • Firstpage
    501
  • Lastpage
    506
  • Abstract
    A scheduling methodology is described for high-level synthesis of designs with a significant amount of control structure. The objective is to utilize all the available resources while scheduling with respect to resource restriction. To do so, a vector/matrix structure is built which provides a global view of resource usage at each node. It supports the migration of operations across basic blocks to wherever idle resources are available. With it, the authors formulate a list scheduling algorithm in which the dispatching priority changes dynamically with respect to resource availability
  • Keywords
    circuit CAD; resource allocation; scheduling; basic blocks; control structure; dispatching priority; global view; high-level synthesis; idle resources; list scheduling algorithm; resource availability; resource restriction; resource usage; scheduling methodology; vector/matrix structure; Availability; Computer science; Concurrent computing; Dispatching; Flow graphs; High level synthesis; Parallel processing; Processor scheduling; Resource management; Scheduling algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1992. Proceedings., [3rd] European Conference on
  • Conference_Location
    Brussels
  • Print_ISBN
    0-8186-2645-3
  • Type

    conf

  • DOI
    10.1109/EDAC.1992.205986
  • Filename
    205986