• DocumentCode
    3099731
  • Title

    A 3.6 mW 1.4 V SRAM with non-boosted, vertical bipolar bitline contact memory cell

  • Author

    Sato, H. ; Nagaoka, H. ; Honda, H. ; Maki, Y. ; Wada, T. ; Arita, Y. ; Tsutsumi, K. ; Yamada, M.

  • Author_Institution
    Mitsubishi Electr. Corp., Itami, Japan
  • fYear
    1998
  • fDate
    5-7 Feb. 1998
  • Firstpage
    352
  • Lastpage
    353
  • Abstract
    Low-voltage SRAMs operating at <3 V are currently used for handy terminals. However, demand for lower-voltage operation has increased. It is difficult to reduce operating voltage below 2.5 V with a conventional low-power SRAM with 4-nMOS-transistor cell. Although a full CMOS cell or a boosted word line technique could reduce operating voltage, they have certain problems, i.e., a larger cell or elaborate timing control for boost. This 256 kb, low-power SRAM uses a bipolar bit line contact (BBC) memory cell, and features small cell, low operating voltage, low power dissipation and fast access.
  • Keywords
    SRAM chips; 1.4 V; 256 kbit; 3.6 mW; SRAM; access time; low-voltage SRAMs; memory cell; operating voltage; power dissipation; vertical bipolar bitline contact; Bipolar transistors; Diodes; Driver circuits; Low voltage; MOSFETs; Power dissipation; Random access memory; Routing; Timing; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-4344-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.1998.672520
  • Filename
    672520