Experimental study to push the Flash floating gate memories toward low energy applications

The problem of energy saving has today a relevant importance, concerning in particular all the portable devices as smart phone, tablet PC, smart card and so on [1]. In order to improve the features of these products, particular attention is paid to energy consumption of Flash cells in memory arrays. In this work we investigated the Flash floating gate (FG) dynamic behavior during the channel hot electron (CHE) programming operation. After this, we propose a solution to optimize the energy consumption. The samples studied in this experimental work are Flash floating gate memory cells (embedded NOR flash process). The ONO inter-poly dielectric stack has an equivalent thickness of 14nm, while the tunnel oxide of 9.5nm is grown on a p-type silicon substrate. We evaluated the variation effect of two important technological parameters: channel doping dose (CDD) and lightly doped drain (LDD) energy implantation.