Principles of operation for a fast, low-voltage digital switch

Reduced energy dissipation in device switching may be the most critical attribute for the success of any new switch which can replace the field effect transistor for digital logic. There are two very distinct physical approaches to this goal. The first approach is to store less energy in the device to distinguish digital logic states. The second approach is to conserve the stored energy from switching event to switching event by implementing near-adiabatic switching protocols and energy-conserving logic circuits. Here I focus on the first approach which is broadly compatible with well-established circuit families. Since the stored energy is 1/2 CV², it is highly desirable to reduce the power supply voltage. However, minimum supply voltages for conventional FETs must be many times kT/e in order to maintain an acceptably large distinction between ON and OFF currents, and are already severely constrained by this limit. Altering the device physics to improve the subthreshold slope is essential for the realization of fast logic at very low voltages. Thermal voltage noise sets the true low-voltage limit for such devices [1], and at room temperature that limit is far below the roughly 1V limit for low-voltage operation of fast FETs of conventional design.