Title :
Four-state FETs incorporating quantum dot gate (QDG), quantum dot channel (QDC) and spatial wavefunction-switched (SWS) structures: Basis for 2-bit processing circuit architectures
Author :
Jain, F. ; Baskar, K. ; Karmakar, S. ; Chan, P.-Y. ; Suarez, E. ; Miller, B. ; Chandy, J. ; Heller, E.
Author_Institution :
ECE Dept., UConn, Storrs, CT, USA
Abstract :
Three-state behavior has been demonstrated in Si and InGaAs FETs when two layers of cladded nanodots (e.g. SiOx-cladded Si or GeOx-cladded Ge) are assembled on the thin tunnel gate insulator. The advantages of 3-state behavior in reducing device count in logic, analog-to-digital converters (ADCs), and DACs has been reported [1]. Unlike three-state QDG-FETs, four-state devices offer significant advantages in reducing device count and power dissipation in multi-valued logic architecture.
Keywords :
III-V semiconductors; analogue-digital conversion; digital-analogue conversion; field effect transistors; gallium arsenide; indium compounds; semiconductor quantum dots; silicon; ADC; DAC; InGaAs; QDC; SWS structures; Si; analog-to-digital converters; cladded nanodots; four-state FET; multivalued logic architecture; power dissipation; processing circuit architectures; quantum dot channel; quantum dot gate; spatial wavefunction-switched structures; thin tunnel gate insulator; three-state QDG-FET; word length 2 bit; FETs; Indium gallium arsenide; Insulators; Logic gates; Quantum dots; Silicon;
Conference_Titel :
Semiconductor Device Research Symposium (ISDRS), 2011 International
Conference_Location :
College Park, MD
Print_ISBN :
978-1-4577-1755-0
DOI :
10.1109/ISDRS.2011.6135287
