Optimized design of UART IP soft core based on DMA mode

This Traditional UART IP hard core is poor at flexibility and transportability while UART IP soft core is only based on poll and interrupt mode at present which consumes so much time of CPU that the performance of embedded system is reduced greatly. UART IP soft core based on DMA mode is proposed and well elaborated using the characteristic of DMA. The IP core is AVALON bus-compatible with the control and arithmetic logic of entire IP core completed by a single FPGA chip so that it is very suited to NIOSII embedded system. Five main sub modules are well designed and the whole IP core is tested and verified in a simple NIOSII embedded hardware system. It turns out that UART IP soft core based on DMA mode can reduce elapsed time of CPU greatly in data transmission process so that the performance of NIOSII system can be improved and design requirement can be better met with less resources occupied, high speed, high flexibility and high transportability.