Programmable demultiplexer/demodulator processor

Low to medium bit rate digital transmission formats are increasingly being used for satellite communications to reduce the size and cost of earth stations. A combined demultiplexer and demodulator using digital signal processing is described which uses frequency domain filtering to separate the signals and a shared structure for the demodulation process. A special-purpose, high-speed fast Fourier transform (FFT) processor is designed which operates on a 20-MHz bandwidth that contains carriers ranging in bit rate from approximately 1.5 to 11.3 Mb/s. An interpolating filter is used between the demultiplexer and the demodulator to provide the two samples per symbol required for the demodulation process. The major components of the demultiplexer/demodulator are described. The implementation concentrated on designs using low-power complementary metal-oxide semiconductor (CMOS) circuitry. In addition, a testbed was designed and fabricated to provide the multicarrier inputs needed to demonstrates system capability