1 Gb/s operation and bit error rate studies of diode-clamped FET-SEED smart pixel receivers

Smart pixel technology is targeted at the realization of large numbers of optical input and output from electronic chips. Two key components of this technology are the receiver and transmitter. Here we discuss the performance of receiver modules based on diode-clamped FET-SEED circuits. We present the operation of diode-clamped receivers with electrical output operating at rates up to 1 Gb/s. Further, we report the first bit error rate testing of this receiver. Since receivers of this type are envisioned to be present in large numbers on electronic processing chips, constraints on power consumption and chip area are present that do not normally bear on the design of conventional telecommunications receivers. Therefore, one may consider the smart pixel receiver to represent a new class of device