Title :
Dual-injection sub-harmonic injection-locked frequency tripler
Author :
Chang-Chun Chen ; Janne-Wha Wu ; Te-Feng Chiao
Author_Institution :
Dept. of Electr. Eng., Nat. Chung-Cheng Univ., Chiayi, Taiwan
Abstract :
This paper presents a sub-harmonic injection-locked frequency tripler. This injection-locked frequency tripler was implemented with TSMC 0.18 μm 1P6M CMOS process. The feature of the proposed circuit employs the way of the dual-injection to lock the triple-frequency signal with higher output power. The available output power after the buffer stage of 0.6 dB gain is -2.88 dBm. The power consumption of the core circuit takes 9.22 mW from a 1.8 V power supply. The measured locking range is from 21.38 GHz to 23.37 GHz.
Keywords :
CMOS integrated circuits; buffer circuits; frequency multipliers; injection locked oscillators; CMOS process; TSMC; buffer stage; core circuit; dual-injection sub-harmonic injection-locked frequency tripler; frequency 21.38 GHz to 23.37 GHz; gain 0.6 dB; power 9.22 mW; power consumption; voltage 1.8 V; Frequency conversion; Gain; Harmonic analysis; Phase noise; Power amplifiers; Power generation; Frequency Tripler; Injection-Locked Oscillator; Multiplier;
Conference_Titel :
Microwave Conference Proceedings (APMC), 2012 Asia-Pacific
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4577-1330-9
Electronic_ISBN :
978-1-4577-1331-6
DOI :
10.1109/APMC.2012.6421873
