Investigation of a high temperature oxide-trap activation model for SiC power MOSFETs

The U.S. Army Research Laboratory is investigating performance and reliability issues associated with the development of n-channel 4H-SiC DMOSFET devices for advanced power conversion systems. The threshold-voltage instability (V_T) effect generally observed in state-of-the-art SiC MOSFETs can be explained by an electron tunneling mechanism, where electrons tunnel in and out of near interfacial oxide traps from the underlying SiC substrate [1]. This effect is very similar to that observed in irradiated Si MOSFETs, and described by the Harry Diamond Laboratory (HDL) Hole Trap Model, which attributed that observed instability to the charging and discharging of an oxide trap associated with an oxygen-vacancy defect - the so-called E ´ center [2]. The pre-cursor site for this trap is a weak Si-Si bond which may be broken by the hole-trapping process. It apparently can also be broken by the application of an electric field at elevated temperature. Recent electron spin resonance (ESR) measurements used to study negative bias temperature instability (NBTI) in Si MOS test structures have shown an increase in the number of these E´ defects with the simultaneous application of both a high-temperature and gate-bias stress [3]. This effect may also explain previous high-temperature gate bias (HTGB) stress testing results of power SiC MOSFETs, including the case of self-heating caused by ON-state current stressing, which revealed a significant increase in the V_T instability [4]. This result was unexpected since the tunneling process is generally insensitive to changes in temperature. However, since recent ESR results in the literature have identified an E´-type oxide defect in SiC MOS-based devices as well [5], it may very well be that additional oxide traps are also being activated under bias at high temperature in SiC MOSFETs.