Hybrid Power Filter with Output Impedance Control

Next-generation microprocessors requires 150 A/0.8 V with slow rates of >70 A/ns. At 10 GHz switching frequencies, the ESL of the packaging capacitors presents more problems than the ESR. This paper highlights a unique hybrid power filter using output impedance matching to allow seamless compatibility of the VRM, packaging capacitors, microprocessor die, and active filter. This topology reduces required capacitors by roughly 90%, with simulations showing <100 mV ripple at projected slew rates. An experimental prototype is demonstrated to suppress undershoot caused by 25 A load transients at 160 A/mus with off-the-shelf components