Custom ASIC development for high-speed Viterbi decoding

A high-speed, emitter-coupled logic (ECL) gate array which greatly facilitates the implementation of very high-speed Viterbi algorithm processors has been developed. These high-speed Viterbi decoders were incorporated into two bandwidth-efficient, jointly optimized coded modulation systems with baseband information rates of 140 and 200 Mbit/s. The 200-Mb/s system was developed for NASA under the Advanced Modulation Technology Development program. The octal phase shift keying (8PSK) modulation technique used in these systems requires symbol rates of 60 to 75 Msymbol/s. The gate array device also has the potential for use in similar systems with symbol rates in excess of 100 Msymbol/s. Some details of the coded modulation systems that require the implementation of high-speed Viterbi processors are provided to demonstrate current practical applications and the need for this processing capability. The specific gate array design is described in conjunction with the performance goals and measured parameters of the completed device